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Woorham Bae Deo Analysis and Design of CMOS Clocking Circuits For Lo (Hardback)

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Book Title
Analysis and Design of CMOS Clocking Circuits For Low Phase Noise
Publication Name
Analysis and Design of Cmos Clocking Circuits for Low Phase Noise
Title
Analysis and Design of CMOS Clocking Circuits For Low Phase Noise
Author
Deog-Kyoon Jeong, Woorham Bae
Format
Hardcover
EAN
9781785618017
ISBN
9781785618017
Publisher
Institution of Engineering & Technology
Genre
Technology & Engineering
Release Year
2020
Release Date
19/08/2020
Language
English
Country/Region of Manufacture
GB
Item Height
234mm
Item Length
9.2 in
Series
Materials, Circuits and Devices Ser.
Subject Area
Technology & Engineering
Subject
Engineering (General), Electronics / Circuits / Integrated
Publication Year
2020
Type
Textbook
Item Width
6.1 in
Number of Pages
256 Pages

關於產品

Product Information

As electronics continue to become faster, smaller and more efficient, development and research around clocking signals and circuits has accelerated to keep pace. This book bridges the gap between the classical theory of clocking circuits and recent technological advances, making it a useful guide for newcomers to the field, and offering an opportunity for established researchers to broaden and update their knowledge of current trends. The book begins by introducing the theory of Fourier transform and power spectral density, then builds on this foundation in chapter 2 to define phase noise and jitter. Chapter 3 discusses the theory and primary implementation of CMOS oscillators, including LC oscillators and ring oscillators, and chapter 4 introduces techniques for analysing their phase noise and jitter. Chapters 5-7 cover conventional clocking circuits; phase-locked loop (PLL) and delay-locked loop (DLL), which suppress the phase noise of CMOS oscillators. The building blocks of conventional PLLs/DLLs are described, and the dynamics of the PLL/DLL negative feedback loop explored in depth, with practical design examples. Chapters 8-11 address state-of-the-art circuit techniques for phase noise suppression, presenting the principles and practical issues in circuit implementation of sub-sampling phase detection techniques, all-digital PLL/DLL, injection-locked oscillator, and clock multiplying DLL. Extensive survey and discussion on state-of-the-art clocking circuits and benchmarks are covered in an Appendix.

Product Identifiers

Publisher
Institution of Engineering & Technology
ISBN-10
1785618016
ISBN-13
9781785618017
eBay Product ID (ePID)
16038665437

Product Key Features

Author
Deog-Kyoon Jeong, Woorham Bae
Publication Name
Analysis and Design of Cmos Clocking Circuits for Low Phase Noise
Format
Hardcover
Language
English
Subject
Engineering (General), Electronics / Circuits / Integrated
Series
Materials, Circuits and Devices Ser.
Publication Year
2020
Type
Textbook
Subject Area
Technology & Engineering
Number of Pages
256 Pages

Dimensions

Item Length
9.2 in
Item Width
6.1 in

Additional Product Features

LCCN
2020-414435
Lc Classification Number
Tk7871.99.M44
Table of Content
Chapter 1: Introduction Chapter 2: Introduction to phase noise and jitter Chapter 3: CMOS oscillators Chapter 4: Phase noise theory for CMOS oscillators Chapter 5: Introduction to PLL/DLL Chapter 6: PLL loop dynamics and jitter Chapter 7: DLL loop dynamics and jitter Chapter 8: Phase noise suppression techniques 1: subsampling PLL Chapter 9: Phase noise suppression techniques 2: all-digital PLL Chapter 10: Phase noise suppression techniques 3: injection locking Chapter 11: Phase noise suppression techniques 4: clock multiplying DLL Appendix A: Figure of merits (FoMs) for evaluating VCOs and PLLs Appendix B: Survey on state-of-the-art clock generators Appendix C: System Verilog modeling of CMOS clock generator including jitter Appendix D: Noise sources in MOSFET transistor
Copyright Date
2020
Target Audience
College Audience
Dewey Decimal
621.39732
Dewey Edition
23
Illustrated
Yes

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