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Igor Tartalja The Cache Coherence Problem In Shared-Memory Multiprocess BOOK NEW
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- Artist
- Igor Tartalja
- EAN
- 9780818670961
- Format
- Trade Paperback
- ISBN
- 9780818670961
- Language
- English
- Release Year
- 1996-01-30
- Book Title
- The Cache Coherence Problem In Shared-Memory Multiprocessors
- Type
- Textbook
- Subject Area
- Computers
- Publication Name
- Caché Coherence Problem in Shared-Memory Multiprocessors : Software Solutions
- Item Length
- 11 in
- Publisher
- Wiley & Sons, Incorporated, John
- Subject
- Programming / General, Systems Architecture / Distributed Systems & Computing, Networking / General, General
- Publication Year
- 1996
- Series
- Systems Ser.
- Item Height
- 0.8 in
- Item Width
- 8.1 in
- Item Weight
- 29.7 Oz
- Number of Pages
- 358 Pages
關於產品
Product Information
Almost all software solutions are developed through academic research and implemented only in prototype machines, thus leaving the field of software techniques for maintaining the cache coherence widely open for new research and development. This book is a collection of all the representative approaches to software coherence maintenance and includes a number of related studies in the performance evaluation field. The illustrates state-of-the-art software solutions for cache coherence maintenance in shared-memory multiprocessors. It begins with a set of four overview of the cache coherence problem and introduces software solutions to the problem. The text defines and details static and dynamic software schemes, techniques for modeling performance evaluation mechanisms, and performance evaluation studies. The book is intended for the experienced reader in computer engineering but possibly a novice in the topic of cache coherence. It also provides an in-depth understanding of the problem as well as a comprehensive overview for multicomputer designers, computer architects, and compiler writers. In addition, it is a software coherence reference handbook for advanced undergraduate and typical graduate students in multiprocessing and multiprogramming areas.
Product Identifiers
Publisher
Wiley & Sons, Incorporated, John
ISBN-10
0818670967
ISBN-13
9780818670961
eBay Product ID (ePID)
771014
Product Key Features
Publication Name
Caché Coherence Problem in Shared-Memory Multiprocessors : Software Solutions
Format
Trade Paperback
Language
English
Subject
Programming / General, Systems Architecture / Distributed Systems & Computing, Networking / General, General
Publication Year
1996
Series
Systems Ser.
Type
Textbook
Subject Area
Computers
Number of Pages
358 Pages
Dimensions
Item Length
11 in
Item Height
0.8 in
Item Width
8.1 in
Item Weight
29.7 Oz
Additional Product Features
LCCN
95-010025
Intended Audience
Scholarly & Professional
Series Volume Number
10
Lc Classification Number
Qa76.9.M45t37 1996
Table of Content
Preface. Introduction. Chapter 1: Introductory Readings. How to Make a Multiprocessor Computer that Correctly Executes Multiprocess Programs (L. Lamport). Synchronization, Coherence, and Event Ordering in Multiprocessors (M. Dubois, C. Scheurich, and F.A. Briggs). Cache Coherence in Large-Scale Shared-Memory Multiprocessors: Issues and Comparisons (D. Lilja). Software Cache Consistency in Shared-Memory Multiprocessors: A Survey of Approaches and Performance Evaluation Studies (I. Tartalja and V. Milutinovic). Chapter 2: Static Software Cache Coherence Schemes. Compiler-Directed Cache Management in Multiprocessors (H. Cheong and A.V. Veidenbaum). RP3 Processor-Memory Element (W.C. Brantley, K.P. McAuliffe, and J. Weiss). A Compiler-Assisted Cache Coherence Solution for Multiprocessors (A.V. Veidenbaum). A Cache Coherence Scheme With Fast Selective Invalidation (H. Cheong and A.V. Veidenbaum). Automatic Management of Programmable Caches (R. Cytron, S. Karlovsky, and K.P. McAuliffe). A Version Control Approach to Cache Coherence (H. Cheong and A.V. Veidenbaum). Design and Analysis of a Scalable Cache Coherence Scheme Based on Clocks and Timestamps (S.L. Min and J.-L. Baer). A Generational Algorithm to Multiprocessor Cache Coherence (T.C. Chiueh). Cache Coherence Using Local Knowledge (E. Darnell and K. Kennedy). Chapter 3: Dynamic Software Cache Coherence Schemes. Software-Controlled Caches in the VMP Multiprocessor (D.R. Cheriton, G.A. Slavenburg, and P.D. Boyle). CPU Cache Consistency with Software Support and Using "One Time Identifiers" (A.J. Smith). An Approach to Dynamic Software Cache Consistency Maintenance Based on Conditional Invalidation (I. Tartalja and V. Milutinovic). Adaptive Software Cache Management for Distributed Shared Memory Architectures (J.K. Bennett, J.B. Carter, and W. Zwaenepoel). Chapter 4: Techniques for Modeling and Performance Evaluation of Cache Memories and Cache Coherence Maintenance Mechanisms. Analysis of Multiprocessors with Private Cache Memories (J.H. Patel). Effectiveness of Private Caches in Multiprocessor Systems with Parallel-Pipelined Memories (F.A. Briggs and M. Dubois). On the Validity of Trace-Driven Simulation for Multiprocessors (E.J. Koldinger, S.J. Eggers, and H.M. Levy). Multiprocessor Cache Simulation Using Hardware Collected Address Traces (A.W. Wilson). Cache Invalidation Patterns in Shared-Memory Multiprocessors (A. Gupta and W.-D. Weber). Benchmark Characterization for Experimental System Evaluation (T.M. Conte and W.W. Hwu). A Model of Workloads and Its Use in Miss-Rate Prediction for Fully Associative Caches (J.P. Singh. H.S. Stone, and D.F. Thiebaut). Chapter 5: Performance Evaluation Studies of Software Coherence Schemes). A Performance Comparison of Directory-Based and Timestamp-Based Cache Coherence Schemes (S.L. Min and J.-L. Baer). Evaluating the Performance of Software Cache Coherence (S. Owicki and A. Agarwal). Comparison of Hardware and Software Cache Coherence Schemes (S.V. Adve, V.S. Adve, M.D. Hill, and M.K. Vernon). About the Author.
Copyright Date
1996
Dewey Decimal
005.4/2
Dewey Edition
20
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