第 1/1 張圖片
Low-Power Optimization of Selected Fpga Blocks by Karol Niewiadomski (English) P
狀況：
庫存 3 件
運費：
所在地：Fairfield, Ohio, 美國
送達日期：
估計於 6月14日, 五至 6月26日, 三之間送達 運送地點 43230
退貨：
保障：
請參閱物品說明或聯絡賣家以取得詳細資料。閱覽全部詳情查看保障詳情
（不符合「eBay 買家保障方案」資格）
安心購物
賣家必須承擔此刊登物品的所有責任。
eBay 物品編號：386988764330
物品細節
- 物品狀況
- 全新: 全新，未閱讀過和使用過的書籍，狀況完好，不存在缺頁或內頁受損。 查看所有物品狀況定義會在新視窗或分頁中開啟
- ISBN-13
- 9783832549473
- Book Title
- Low-Power Optimization of Selected Fpga Blocks
- ISBN
- 9783832549473
- Publication Year
- 2019
- Type
- Textbook
- Format
- Trade Paperback
- Language
- English
- Publication Name
- Low-Power Optimization of Selected FPGA Blocks
- Item Length
- 8.3in
- Publisher
- Logos Verlag Berlin
- Item Width
- 5.7in
- Item Weight
- 26.9 Oz
- Number of Pages
- 217 Pages
關於產品
Product Information
Reconfigurable logic can offer a wide range of flexibility for different applications. Since the introduction of the first FPGAs by a number of different companies, they were used as glue logic to connect different components of an entire system. In the following years, fast prototyping has led to new possibilities of firmware development running in parallel to IC design, and because of that, the development time has been reduced significantly and products can enter the market at an earlier point of time. However, these special ICs cannot compete with ASICs in mass production due to their high production costs which consequently limits their application to cost sensitive markets e.g. for being used in automotive applications. This has led various FPGA vendors to develop low-end FPGAs for countering the price advantage of ASICs and to raise the attractiveness of these chips in the automotive industry. Despite many advantages of reconfigurable logic, cost-optimized FPGAs lack of efficient power saving mechanisms which is a necessary feature in applications with limited energy resources. The scope of this thesis is the research on the implementation of dedicated power saving logic on selected blocks within a FPGA. These blocks were analyzed based on the choice of a commercial baseline architecture and re-engineered to significantly cut-down the average power consumption and related leakage currents. The affected blocks were SRAM cells, D-FFs and I/O elements, which consume a comparably large area footprint of the FPGA fabric and therefore depict a good target for optimization and modification. Specific characteristics like SNM, WNM, maximum frequency and high impedance were also considered and evaluated against the baseline design as well as compared against selected solutions from related academic research.
Product Identifiers
Publisher
Logos Verlag Berlin
ISBN-10
3832549471
ISBN-13
9783832549473
eBay Product ID (ePID)
28038413383
Product Key Features
Publication Name
Low-Power Optimization of Selected FPGA Blocks
Format
Trade Paperback
Language
English
Publication Year
2019
Type
Textbook
Number of Pages
217 Pages
Dimensions
Item Length
8.3in
Item Width
5.7in
Item Weight
26.9 Oz
Additional Product Features
Target Audience
College Audience
Topic
Computer Science, Electronics / General
Genre
Computers, Technology & Engineering
賣家提供的物品說明
賣家必須承擔此刊登物品的所有責任。
eBay 物品編號：386988764330
運費與處理費
物品所在地：
Fairfield, Ohio, 美國
運送地點
全球
排除：
APO/FPO, 俄羅斯聯邦, 利比亞, 委內瑞拉, 巴布亞新畿內亞, 巴拿馬, 巴貝多, 新喀里多尼亞, 法屬圭亞那, 法屬玻里尼西亞, 烏克蘭, 瓜德羅普島, 留尼汪島, 白俄羅斯, 美國領地, 西薩摩亞, 阿拉斯加／夏威夷, 馬提尼克島
| 運費與處理費 | 每加一件物品 | 運送地點 | 運送方式 | 運送*查看送達備註 |
|---|---|---|---|---|
| 免運費 | 免費 | 美國 | Economy Shipping | 估計於 6月14日, 五至 6月26日, 三之間送達 運送地點 43230 |
| 處理時間 |
|---|
| 通常會在收到所有款項後的 10 個工作日內發貨。 |
| 稅項 |
|---|
| 結賬時相關稅項可能適用。 進一步了解進一步了解為 eBay 購物繳稅。 |
物品編號 386988764330 的銷售稅
物品編號 386988764330 的銷售稅
賣家會對寄往以下各州的物品收取銷售稅：
| 州／省 | 銷售稅稅率 |
|---|
退貨政策
| 收到物品後聯絡賣家的期限： | 退款方式 |
|---|---|
| 30 日 | 退款 |
買家負責支付退貨運費。
賣家信用評價 （1,023,979）
5***1 (218)- 買家留下的信用評價。
過去 1 個月
購買已獲認證
AAAA+
1***e (521)- 買家留下的信用評價。
過去 1 個月
購買已獲認證
Very fast service, item in excellent condition..
1***e (521)- 買家留下的信用評價。
過去 1 個月
購買已獲認證
Very fast service, item in excellent condition.